FPGA 80386 implementation shows how the old chip kept memory fast

Revival on an FPGA

It has been reported that developer nand2mario has gotten an FPGA implementation of the Intel 80386 to boot DOS, run utilities like Norton Commander, and even play Doom — all on a DE10‑Nano at about 75 MHz. That’s a delicious little victory for retro-hardware fans: not just blinking LEDs, but real software, running on a real reconstructed microarchitecture. It feels like archaeology with solder and HDL; you can almost hear the boot prompt.

Inside the 80386 memory pipeline

The blog post digs into one of the 386’s trickiest bits: the memory pipeline. On paper, x86 virtual memory looks horrendously slow — effective address calc, segmentation, limit checks, TLB lookups, and page‑table walks, often with Accessed/Dirty updates. Yet Intel’s own 1986 work (and Jim Slager’s Performance Optimizations of the 80386) claimed the common path cost only about 1.5 clocks. How? By overlapping work. The 80386 doesn’t do all checks serially; it precomputes, pipelines, and runs pieces in parallel so a read (RD), write (WR) and the microcode’s DLY slots only bite a tiny fraction of the cycle budget. The post walks through microcode snippets and explains how those tiny RD/WR hooks stay cheap in silicon.

Why it matters

This isn’t just nostalgia. Recreating the 80386 in RTL and timing it on modern FPGAs teaches why microarchitectural tricks matter — and why a design from the mid‑1980s still looks elegant today. It has been reported that the project exposes the microcode-driven control flow and the dedicated address path Intel used to make virtual memory fast, which is both an educational roadmap and a reminder: performance is as much about clever overlaps as raw clock speed. For hackers, historians, and engineers, that overlap is the emotional core here — seeing complexity made humane again.

Sources: nand2mario.github.io, Hacker News